IndustrialControlSystems.Logical.Timers

This package contains various types of timers.

Information

  

Description

This package contains a list of models representing various timer.

Extends from Modelica.Icons.Package (Icon for standard packages).

Package Content

NameDescription
IndustrialControlSystems.Logical.Timers.Timer_On Timer_On ON timer model
IndustrialControlSystems.Logical.Timers.Timer_On_Redge Timer_On_Redge ON timer model, active on rising edge
IndustrialControlSystems.Logical.Timers.Timer_OffDelay Timer_OffDelay OFF delay timer model
IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Redge Timer_OffDelay_Redge OFF delay timer model, active on rising edge
IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Fedge Timer_OffDelay_Fedge OFF delay timer model, active on falling edge
IndustrialControlSystems.Logical.Timers.Functions Functions Functions
IndustrialControlSystems.Logical.Timers.Interfaces Interfaces Interfaces
IndustrialControlSystems.Logical.Timers.Examples Examples Examples

IndustrialControlSystems.Logical.Timers.Timer_On IndustrialControlSystems.Logical.Timers.Timer_On

ON timer model

Information

    

Description

The timer is active when the Set signal ( S ) is true.
The output ( Q ) of the timer rises up when S becomes true and remains high for PV seconds.
If the Set signal become false while counting, the timer stops and the output become false.
If the Reset signal ( R ) becomes true, the output becomes false and the timer stops.

Images show:



Extends from IndustrialControlSystems.Logical.Timers.Interfaces.BaseResidualTimer (Partial interface of a generic timer with residual time output).

Parameters

NameDescription
TsSampling time [s]

Connectors

NameDescription
SSet signal
RReset signal
PVtimer Programmed Value
Qstatus of the timer
trresidual time

IndustrialControlSystems.Logical.Timers.Timer_On_Redge IndustrialControlSystems.Logical.Timers.Timer_On_Redge

ON timer model, active on rising edge

Information

  

Description

The timer is actived when the set signal ( S ) becomes true (on the rising edge of S ).
The output ( Q ) of the timer rises up when S becomes true and remains high for PV seconds.
If the Set signal become false while counting, the timer does not stop.
If the reset signal ( R ) becomes true (a rising edge is detected) the output becomes false and the timer stops.

Images show:



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Extends from IndustrialControlSystems.Logical.Timers.Interfaces.BaseResidualTimer (Partial interface of a generic timer with residual time output).

Parameters

NameDescription
TsSampling time [s]

Connectors

NameDescription
SSet signal
RReset signal
PVtimer Programmed Value
Qstatus of the timer
trresidual time

IndustrialControlSystems.Logical.Timers.Timer_OffDelay IndustrialControlSystems.Logical.Timers.Timer_OffDelay

OFF delay timer model

Information

  

Description

The timer is active after the set signal ( S ) becomes true.
The output ( Q ) of the timer rises up PV seconds after the Set ( S ) becomes true.
If the Set signal becomes false while counting, the timer stops and the output remains false.
If the Reset signal ( R ) becomes true, the output remains false and the timer stops.

Images show:

  

Extends from IndustrialControlSystems.Logical.Timers.Interfaces.BaseResidualTimer (Partial interface of a generic timer with residual time output).

Parameters

NameDescription
TsSampling time [s]

Connectors

NameDescription
SSet signal
RReset signal
PVtimer Programmed Value
Qstatus of the timer
trresidual time

IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Redge IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Redge

OFF delay timer model, active on rising edge

Information

  

Description

The timer is active after a rising edge of the set signal ( S ).
The output ( Q ) of the timer rises up PV seconds after the Set ( S ) becomes true.
If the Set signal become false while counting, the timer does not stop.
If the Reset signal ( R ) becomes true, the output remains false and the timer stops.

Images show:



Extends from IndustrialControlSystems.Logical.Timers.Interfaces.BaseResidualTimer (Partial interface of a generic timer with residual time output).

Parameters

NameDescription
TsSampling time [s]

Connectors

NameDescription
SSet signal
RReset signal
PVtimer Programmed Value
Qstatus of the timer
trresidual time

IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Fedge IndustrialControlSystems.Logical.Timers.Timer_OffDelay_Fedge

OFF delay timer model, active on falling edge

Information

  

Description

The timer is active after a falling edge of the set signal ( S ).
The output ( Q ) of the timer rises up PV seconds after the Set ( S ) becomes false (falling edge).
If the Set signal become true while counting, the timer does not stop.
If the Reset signal ( R ) has a rising edge, the output remains false and the timer stops.

Images show:



Extends from IndustrialControlSystems.Logical.Timers.Interfaces.BaseResidualTimer (Partial interface of a generic timer with residual time output).

Parameters

NameDescription
TsSampling time [s]

Connectors

NameDescription
SSet signal
RReset signal
PVtimer Programmed Value
Qstatus of the timer
trresidual time

Automatically generated Mon May 21 13:34:13 2012.