This package contains a list of basic and customisable logical elements.
Extends from Modelica.Icons.Package (Icon for standard packages).
Name | Description |
---|---|
![]() | Model of a n-bit NOT |
![]() | Model of a n-bit AND |
![]() | Model of a n-bit NAND |
![]() | Model of a n-bit OR |
![]() | Model of a n-bit NOR |
![]() | Model of a n-bit XOR |
![]() | Model of a n-bit XNOR |
![]() | Model of a Set-reset Flip Flop |
![]() | Package that contains the set of functions used by the logical operations |
![]() | Interfaces |
![]() | Examples |
Model of a n bit NOT gate.
The number of the input (nInput) signals must be equal to the number of output (nOutput) signals.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a n bit AND gate.
The number of the input (nInput) signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a n bit NAND gate.
The number of the input (nInput) signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a n bit OR gate.
The number of the input (nInput) signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a n bit NOR gate.
The number of the input (nInput) signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a n bit XOR gate.
The number of the input (nInput) signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a n bit XNOR gate.
The number of the input (nInput) signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
Ts > 0it behaves as a discrete time system,
Ts <= 0it behaves as a continous time system. No delay is introduced and events are generated when the output changes (this mode reduces the simulation time)
Extends from IndustrialControlSystems.Logical.LogicalOperations.Interfaces.LogicalBlock (Partial interface of a generic nInput nOutput logical block).
Name | Description |
---|---|
Ts | sampling time |
nInput | number of inputs |
nOutput | number of outputs |
Name | Description |
---|---|
u[nInput] | input vector |
y[nOutput] | output vector |
Model of a Set Reset Flip Flop.
The inputs and outputs follows
Name | Description |
---|---|
u1 | Set |
u2 | Reset |
y1 | Q |
y2 | not Q |
Behaviour of the FlipFlop, at each time step Ts the inputs are read and the new output Q
is computed starting from the S and R value as well the old value of the output
QOLD.
Set | Reset | Q |
---|---|---|
0 | 0 | QOLD |
0 | 1 | 0 |
1 | 0 | 1 |
1 | 1 | not QOLD |
Extends from Interfaces.LogicalBlock2x2 (partial interface of a generic 2x2 logical block).
Name | Description |
---|---|
Ts | sampling time |
q_start | Output initial value |
Name | Description |
---|---|
u1 | input |
y1 | output |
u2 | input |
y2 | output |